hi
Having constructed an engineering specification of a 32 bit
microprocessor http://indi.hpsdr.com
and check the 32 bit architecture
section, the point has arrived to go forward with the design. Due to
lack of facilities I do not think I will be doing this myself. So a
research call goes out.
I think the design has a number of significant advantages over current
ISAs.
1) Low transistor count so that a larger percentage of silicon is
active per instruction.
2) A new ALU delay flow model for data re-ordering.
3) A very compact ISA with low memory management overheads.
4) A unique divide and multiply using identical logic, but has a non-
commutative multipolication setup of x*(y+1) , and i wonder how 1
relates to c and ih(2pi) quantum non commutivity (simulation speeds??)
also (a~*b)~*c and a~*(b~*c) as group generators of the ring/field (as
div included)
5) Using ForCC codes to locate processing as what done beats where/dns
for locating nodes.
6) ASIC interface defined in ISA.
UK, London would be best, but I can be telework flexible in this
modern age.
cheers
